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TLE4473GV55-2 bảng dữ liệu(PDF) 2 Page - Infineon Technologies AG |
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TLE4473GV55-2 bảng dữ liệu(HTML) 2 Page - Infineon Technologies AG |
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2 / 17 page ![]() Data Sheet 2 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 The device features a reset with adjustable power on delay for each of the outputs. In addition the output for the microcontroller supply comes up with a watchdog in order to supervise a connected microcontroller Reset and Watchdog Behavior The reset output RO2 is in high-state if the voltage on the delay capacitor C D2 is greater or equal V DU2. The delay capacitor CD2 is charged with the current IDC2 for output voltages greater than the reset threshold V RT2. If the output voltage gets lower than VRT2 (‘reset condition’) a fast discharge of the delay capacitor C D2 sets in and as soon as VD2 gets lower than V DL2 the reset output RO2 is set to low-level. The time for the delay capacitor charge is the reset delay time. For the power-on case the charging process of C D2 starts from 0 V, which leads to the equation: (1) for the power-on reset delay time. When the voltage on the delay capacitor has reached V DU2 and reset was set to high, the watchdog circuit is enabled and discharges C D2 with the constant current IDD2. If there is no rising edge observed at the watchdog input, C D2 will be discharge down to V DL2. Then reset output RO2 will be set to low and CD2 will be charged again with the current I DC2 until VD2 reaches VDU2 and reset will be set high again. If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge period C D2 is charged again and the reset output stays high. After VD2 has reached VDU2, the periodical cycle starts again. The watchdog timing is shown in Figure 1. The maximum duration between two watchdog pulses corresponds to the minimum watchdog trigger time T WI,tr. Higher capacitances on pin D2 result in longer watchdog trigger times: (2) If the output voltage Q1 decreases below V RT1 (typ. 4.65 V), the external capacitor CD1 is discharged by the reset generator of the main output. If the voltage on this capacitor drops below V DL1, a reset signal is generated on pin 2 (RO1). If the output voltage rises above the reset threshold, C D1 will be charged with the constant current IDC1. After the power-on-reset time the voltage on the capacitor reaches V DU1 and the reset output will be set high again. The value of the power-on-reset time can be set within a wide range depending of the capacitance of C D1 using the above given equation (1) analogous for Q1. tDon , CD2 VDU2 × IDC2 ----------------------------- = TWI,tr max 0.34 ms/nF CD2 × = |
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