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RD0801

9. Functional Description

When power is turned on, the IRS2530D first starts in Under Voltage Lockout (UVLO)

mode. The UVLO mode is designed to maintain an ultra-low (<250 A) supply current,

and to guarantee that the IC is fully functional before the high- and low-side output (HO

and LO) gate drivers are activated. During UVLO, HO is ‘low’, and VCO is pulled down

to COM for resetting the starting frequency to the maximum. LO is open circuit, and is

used as a shutdown/reset input function for automatically restarting the IC when a lamp

has been removed and re-inserted.

Once VCC reaches the startup threshold (VCCUV+) and the LO pin is below VLOSD-

(lamp is inserted), the half-bridge FETs start to oscillate and the IC enters

frequency ramps down towards the resonant frequency of the high-Q ballast output

stage, causing the lamp voltage to increase. During this time, the filaments of the lamp

are pre-heated to their emission temperature to minimize the necessary ignition voltage

and to increase lamp life. The voltage on pin VCO continues to increase and the

frequency keeps decreasing until the lamp ignites. If the lamp ignites successfully, the

IRS2530D enters the DIM mode. The resonant output stage transitions to a series-L,

parallel RC circuit with the Q-value and operating point determined by the user dim level

(Figure 9.1)

High-Q

Low-Q

Start

Ignition

Vout

Vin

Frequency

fmax

f100%

f10%

f50%

10%

50%

100%

fmin

Figure 9.1: Resonant tank Bode plot with lamp dimming operating points