Data Sheet

27

Rev. 1.0, 2008-10-30

TLE7239GS

Serial Peripheral Interface (SPI)

9

Serial Peripheral Interface (SPI)

The diagnosis and control interface is based on a serial peripheral interface (SPI).

The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is

transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning

of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising

edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is

taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.

Figure 8

Serial Peripheral Interface

The SPI protocol is described in Section 9.3. It is reset to the default values after reset.

9.1

SPI Signal Description

CS - Chip Select: The system micro controller selects the TLE7239GS by means of the CS pin. Whenever the

pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are

ignored and SO is forced into a high impedance state.

CS High to Low transition:

•

The diagnosis information is transferred into the shift register.

•

SO changes from high impedance state to high or low state depending on the logic OR combination between

the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,

a high signal indicates a faulty transmission. For details, please refer to Figure 9. This information stays

available to the first rising edge of SCLK.

Figure 9

Transmission Error Flag on SO Line

LSB

6

5

4

3

2

1

LSB

6

5

4

3

2

1

CS

MSB

MSB

SO

SI

CS

SCLK

time

SPI.emf

TER.emf

SI

SPI

OR

TER

0

1

SO

CS

SCLK

S

SO

S

SI