STM32F103CBT7TR datasheet(67/96 Pages) STMICROELECTRONICS

67 / 96 page

STM32F103x8, STM32F103xB

Electrical characteristics

Doc ID 13587 Rev 12

67/96

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 9.

Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO).

Table 41.

SPI characteristics(1)

Remapped SPI1 characteristics to be determined.

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

DuCy(SCK)

SPI slave input clock

duty cycle

Slave mode

tsu(NSS)

(2)

Based on characterization, not tested in production.

NSS setup time

Slave mode

4tPCLK

th(NSS)

(2)

NSS hold time

Slave mode

2tPCLK

tw(SCKH)

(2)

tw(SCKL)

(2) SCK high and low time

Master mode, fPCLK = 36 MHz,

presc = 4

tsu(MI)

(2)

tsu(SI)

(2)

Data input setup time

Master mode

Slave mode

th(MI)

(2)

Data input hold time

Master mode

th(SI)

(2)

Slave mode

ta(SO)

(2)(3)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

Data output access

time

Slave mode, fPCLK = 20 MHz

3tPCLK

tdis(SO)

(2)(4)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

Data output disable

time

Slave mode

tv(SO)

(2)(1) Data output valid time Slave mode (after enable edge)

tv(MO)

(2)(1) Data output valid time Master mode (after enable edge)

th(SO)

(2)

Data output hold time

Slave mode (after enable edge)

th(MO)

(2)

Master mode (after enable edge)

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