74ACT715S-RSC datasheet(15/18 Pages) FAIRCHILD

15 / 18 page

www.fairchildsemi.com

74ACT715, 74ACT715-R Rev. 1.3

Additional Applications Information

Powering Up

The ACT715 default value for Bit 10 of the Status Regis-

ter is 0. This means that when the CLEAR pulse is

applied and the registers are initialized by loading the

default values the CLOCK is disabled. Before operation

can begin, Bit 10 must be changed to a 1 to enable

CLOCK. If the default values are needed (no other pro-

gramming is required) then Figure 7 illustrates a hard-

wired solution to facilitate the enabling of the CLOCK

after power-up. Should control signals be difficult to

obtain, Figure 8 illustrates a possible solution to auto-

matically enable the CLOCK upon power-up. Use of the

ACT715-R eliminates the need for most of this circuitry.

Modifications of the Figure 8 circuit can be made to

obtain the lone CLEAR pulse still needed upon power-up.

Note that, although during a Vectored Restart none of

the preprogrammed registers are affected, some signals

are affected for the duration of one frame only. These

signals are the Horizontal and Vertical Drive signals.

After a Vectored Restart the beginning of these signals

will occur at the first CLK. The end of the signals will

occur as programmed. At the completion of the first

frame, the signals will resume to their programmed start

and end time.

Preprogramming “On-the-Fly”

Although the ACT715 and ACT715-R are completely

programmable, certain limitations must be set as to

when and how the parts can be reprogrammed. Care

must be taken when reprogramming any End Time reg-

isters to a new value that is lower than the current value.

Should the reprogramming occur when the counters are

at a count after the new value but before the old value,

then the counters will continue to count up to 4096

before rolling over.

For this reason one of the following two precautions are

recommended when reprogramming “on-the-fly”. The

first recommendation is to reprogram horizontal values

during the horizontal blank interval only and/or vertical

values during the vertical blank interval only. Since this

would require delicate timing requirements the second

recommendation may be more appropriate.

The second recommendation is to program a Vectored

Restart as the final step of reprogramming. This will

ensure that all registers are set to the newly pro-

grammed values and that all counters restart at the first

CLK position. This will avoid overrunning the counter

end times and will maintain the video integrity.

Figure 7. Default RS170 Hardwire Conﬁguration

74ACT715S-RSC bảng dữ liệu(PDF) 15 Page - Fairchild Semiconductor

74ACT715S-RSC bảng dữ liệu(HTML) 15 Page - Fairchild Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

bảng dữ liệu tải về

Link URL