©2009 CADEKA Microcircuits LLC

www.cadeka.com

25

Data Sheet

Table 16. Register Values with Corresponding Change in Full-Scale Range

fs_cntrl <5:0>

Full-Scale Range Adjustment

111111

+9.7%

...

...

100001

+0.3%

100000

+0%

011111

-0.3%

...

...

000000

-10%

Table 17. Clock Frequency

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

clk_freq<1:0>

Input clock frequency

50 - 80MHz

X X

56

To optimize startup time a register is provided where the input clock frequency can be set. Some internal circuitry has

startup times that are frequency independent. Default counter values are set to accommodate these startup times at

the maximum clock frequency. This will lead to increased startup times at low clock frequency. Setting the value of this

register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual

startup time, such that the startup time will be reduced. The start up times from Power Down mode and Deep Sleep

mode are changed by this register setting.

Table 18. Clock Frequency Settings

clk_freq <1:0>

Clock Frequency (MHz)

Startup Delay (clock cycles)

Startup Delay (μs)

00

50 - 80

992

12.4 - 19.8

01

32.5 - 50

640

12.8 - 19.7

10

20 - 32.5

420

12.9 - 21

11

15 - 20

260

13 - 17.3

Table 19. Performance Control

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

perfm_

cntrl<2:0>

ADC performance control

Nominal

X X X

50

ext_vcm_

bc<1:0>

VCM buffer driving strength

control

Nominal

X X

There are two registers that impact performance and power dissipation.

The

perfm_cntrl register adjusts the performance level of the ADC core. If full performance is required, the nominal

setting must be used. The lowest code can be used in situations where power dissipation is critical and performance is

less important. For most conditions the performance at the minimum setting will be similar to nominal setting. However,

only 10-bit performance can be expected at worst case conditions. The power dissipation savings shown in Table 20 are

only approximate numbers for the ADC current alone.