M41ST87Y_10 datasheet(23/52 Pages) STMICROELECTRONICS

23 / 52 page

M41ST87Y, M41ST87W

Operating modes

Doc ID 9497 Rev 8

23/52

negative voltage generated by the charge pump during a tamper condition, and from being

pulled to ground by the output of the charge pump when it is in shut-down mode (SHDN =

logic low). The gates of both MOSFETs should be connected to TPCLR as shown in

Figure 20 on page 25. One n-channel enhancement MOSFET should be placed between

the output of the inverting charge pump and the VOUT of the M41ST87. The other MOSFET

should be an enhancement mode p-channel, and placed between VOUT of the M41ST87

and VCC of the external SRAM. When TPCLR goes high after a tamper condition occurs, the

n-channel MOSFET will turn on and the p-channel will turn off. During normal operating

conditions, TPCLR will be low and the p-channel will be on, while the n-channel will be off.

Table 4.

Tamper detection current (normally closed - TCMX = '0')

Figure 17.

Tamper detect sampling options

TDSX

TCHI/TCLOX

Tamper circuit mode

Current at 3.0 V (typ)(1)(2)

When calculating battery lifetime, this current should be added to IBAT current listed in Table 17 on page 44.

Per tamper detect input

Unit

Continuous monitoring / 10 M

Ω pull-up/-down

0.3

µA

Continuous monitoring / 1 M

Ω pull-up/-down

3.0

µA

Sampling (1Hz) / 10 M

Ω pull-up/-down

0.3

Sampling (1Hz) / 1 M

Ω pull-up/-down

3.0

AI07819

TAMPER LO,

NORMALLY OPEN

TAMPER HI,

NORMALLY CLOSED

User

Configuration

TDS

X = 0

TDS

X = 1

TDS

X = 0

TDS

X = 1

TAMPER HI,

NORMALLY OPEN

TAMPER LO,

NORMALLY CLOSED

CONTINUOUS

MONITORING

CONTINUOUS

MONITORING

CONTINUOUS

MONITORING

SAMPLED

MONITORING

CONTINUOUS

MONITORING

SAMPLED

MONITORING

VCC (VOUT)

TCM

X, TPMX

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