80333 datasheet(13/75 Pages) INTEL

13 / 75 page

80333

Datasheet

Intel® 80333 I/O Processor Datasheet

May 2005

Order Number: 305433, Revision: 002

2.7

DMA Controller

The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents

and the local memory. Two separate DMA channels accommodate data transfers to the PCI bus.

Both channels include a local memory to local memory transfer mode. The DMA Controller

supports chaining and unaligned data transfers. It is programmable through the Intel XScale

® core

only.

2.8

I2C Bus Interface Unit

The I

2C (Inter-Integrated Circuit) Bus Interface Unit allows the Intel XScale® core to serve as a

master and slave device residing on the I

2C bus. The I2C unit uses a serial bus developed by Philips

Semiconductor*, consisting of a two-pin interface. The bus allows the 80333 to interface to other

2C peripherals and microcontrollers for system management functions. It requires a minimum of

hardware components for an economical system to relay status and reliability information on the

I/O subsystem to an external device. Also refer to I

2C Peripherals for Microcontrollers (Philips

Semiconductor).

The 80333 includes two I

2C bus interface units.

2.9

Messaging Unit

The Messaging Unit (MU) provides data transfer between the PCI system and the 80333. It uses

interrupts to notify each system when new data arrives. The MU has four messaging mechanisms:

• Message Registers

• Doorbell Registers

• Circular Queues

• Index Registers

Each messaging mechanism allows a host processor or external PCI device and the 80333 to

communicate through message passing and interrupt generation.

2.10

Internal Bus

The Internal Bus is a high-speed interconnect between internal units and Intel XScale

® core

processor. The Internal Bus operates at 333 MHz and is 64 bits wide.

2.11

UART Units

The 80333 includes two UART unit. The UART units allow the Intel XScale

® core to serve as a

master and slave device residing on the UART bus. The UART units use a serial bus consisting of a

four-pin interface. The bus allows the 80333 to interface to other peripherals and microcontrollers.

Also refer to 16550 Device Specification (National Semiconductor*).

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