Z520 datasheet(13/73 Pages) INTEL

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Low Power Features

Datasheet

Low Power Features

2.1

Clock Control and Low-Power States

The processor supports low power states at the thread level and the core/package

level. Thread states (TCx) loosely correspond to ACPI processor power states (Cx). A

thread may independently enter the TC1/AutoHALT, TC1/MWAIT, TC2, TC4, or TC6

low power states, but this does not always cause a power state transition. Only when

both threads request a low-power state (TCx) greater than the current processor state

will a transition occur. The central power management logic ensures the entire

processor enters the new common processor power state. For processor power states

higher than C1, this would be done by initiating a P_LVLx (P_LVL2 and P_LVL3) I/O

read to the chipset by both threads. Package states are states that require external

intervention and typically map back to processor power states. Package states for the

processor include Normal (C0, C1), Stop Grant and Stop Grant Snoop (C2), Deeper

Sleep (C4), and Deep Power Down Technology (C6).

The processor implements two software interfaces for requesting low power states:

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI

P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O

reads are converted to equivalent MWAIT C-state requests inside the processor and do

not directly result in I/O reads on the processor FSB. The monitor address does not

need to be setup before using the P_LVLx I/O read interface. The sub-state hints used

for each P_LVLx read can be configured in a software programmable MSR by BIOS. If

a thread encounters a chipset break event while STPCLK# is asserted, then it asserts

the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to

system logic that individual threads should return to the C0 state and the processor

should return to the Normal state.

Figure 1 shows the thread low-power states. Figure 2 shows the package low-power

states. Table 2 provides a mapping of thread low-power states to package low power

states.

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