E2000 datasheet(65/104 Pages) INTEL

65 / 104 page

Land Listing and Signal Descriptions

Datasheet

BPM[5:0]#

Input/

Output

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals. They are outputs from the processor which indicate

the status of breakpoints and programmable counters used for

monitoring processor performance. BPM[5:0]# should connect the

appropriate pins/lands of all processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.

PRDY# is a processor output used by debug tools to determine

processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP

port. PREQ# is used by debug tools to request debug operation of

the processor.

These signals do not have on-die termination. Refer to Section 2.6.2

for termination requirements.

BPRI#

Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the processor FSB. It must connect the appropriate pins/lands of all

processor FSB agents. Observing BPRI# active (as asserted by the

priority agent) causes all other agents to stop issuing new requests,

unless such requests are part of an ongoing locked operation. The

priority agent keeps BPRI# asserted until all of its requests are

completed, then releases the bus by de-asserting BPRI#.

BR0#

Input/

Output

BR0# drives the BREQ0# signal in the system and is used by the

processor to request the bus. During power-on configuration this

signal is sampled to determine the agent ID = 0.

This signal does not have on-die termination and must be

terminated.

BSEL[2:0]

Output

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select

the processor input clock frequency. Table 16 defines the possible

combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor,

chipset and clock synthesizer. All agents must operate at the same

frequency. For more information about these signals, including

termination recommendations refer to Section 2.8.2.

COMP8

COMP[3:0]

Analog

COMP[3:0] and COMP8 must be terminated to VSS on the system

board using precision resistors.

Table 25.

Signal Description (Sheet 2 of 9)

Name

Type

Description

E2000 bảng dữ liệu(PDF) 65 Page - Intel Corporation

E2000 bảng dữ liệu(HTML) 65 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL