910GL datasheet(164/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

164

Datasheet

8.1.47

PVCCAP2—Port VC Capability Register 2 (D1:F0)

PCI Device:

Address Offset:

108h

Default Value:

00000001h

Access:

Size:

32 bits

This register describes the configuration of PCI Express Virtual Channels associated with this

port.

Bit

Access &

Default

Description

31:24

00h

VC Arbitration Table Offset: This field indicates the location of the VC Arbitration

Table. This field contains the zero-based offset of the table in DQWORDS (16

bytes) from the base address of the Virtual Channel Capability Structure. A value

of 0 indicates that the table is not present (due to fixed VC priority).

23:8

Reserved

7:0

01h

VC Arbitration Capability: This field indicates that the only possible VC

arbitration scheme is hardware fixed (in the root complex).

VC1 is the highest priority, VC0 is the lowest priority.

8.1.48

PVCCTL—Port VC Control (D1:F0)

PCI Device:

Address Offset:

10Ch

Default Value:

0000h

Access:

R/W

Size:

16 bits

Bit

Access &

Default

Description

15:4

Reserved

3:1

R/W

000b

VC Arbitration Select: This field will be programmed by software to the only

possible value as indicated in the VC Arbitration Capability field. The value 001b

when written to this field will indicate the VC arbitration scheme is hardware fixed

(in the root complex).

This field can not be modified when more than one VC in the LPVC group is

enabled.

Reserved

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