910GL datasheet(110/426 Pages) INTEL

110 / 426 page

EPBAR Registers—Egress Port Register Summary

110

Datasheet

6.1.1

EPESD—EP Element Self Description

MMIO Range:

EPBAR

Address Offset:

044h

Default Value:

00000201h

Access:

R/WO, RO

Size:

32 bits

This register provides information about the root complex element containing this Link

Declaration capability.

Bit

Access

& Default

Description

31:24

00h

Port Number: This field specifies the port number associated with this element with

respect to the component that contains this element. A value of 00h indicates to

configuration software that this is the default egress port.

23:16

R/WO

00h

Component ID: This field identifies the physical component that contains this Root

Complex Element. Component IDs start at 1.

This value is a mirror of the value in the Component ID field of all elements in this

component. The value only needs to be written in one of the mirrored fields and it

will be reflected everywhere that it is mirrored.

15:8

02h

Number of Link Entries: This field indicates the number of link entries following

the Element Self Description. This field reports 2 (one each for PCI Express* x16

interface and DMI).

7:4

Reserved

3:0

Element Type: This field Indicates the type of the Root Complex Element.

1h = Port to system memory

910GL bảng dữ liệu(PDF) 110 Page - Intel Corporation

910GL bảng dữ liệu(HTML) 110 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL