M48T59V datasheet(8/32 Pages) STMICROELECTRONICS

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Operation modes

M48T59, M48T59Y, M48T59V

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Operation modes

As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock

oscillator of the M48T59/Y/V are integrated on one silicon chip.

The two circuits are interconnected at the upper eight memory locations to provide user

accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The

clock locations contain the century, year, month, date, day, hour, minute, and second in 24

hour BCD format (except for the century). Corrections for 28, 29 (leap year - valid until

2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control

calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory

locations consisting of BiPORT™ READ/WRITE memory cells. The M48T59/Y/V includes a

clock control circuit which updates the clock bytes with current information once per second.

The information can be accessed by the user in the same manner as any other location in

the static memory array.

The M48T59/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly

monitors the single 5V/3.3 V supply for an out of tolerance condition. When VCC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

midst of unpredictable system operation brought on by low VCC. As VCC falls below the

Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which

maintains data and clock operation until valid power returns.

Table 2.

Operating modes

Note:

X = VIH or VIL; VSO = Battery back-up switchover voltage.

2.1

Read mode

The M48T59/Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip

Enable) is low. The unique address specified by the 13 address inputs defines which one of

the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins

within Address Access time (tAVQV) after the last address input signal is stable, providing

that the E and G access times are also satisfied. If the E and G access times are not met,

valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output

Enable Access time (tGLQV).

Mode

VCC

DQ7-DQ0

Power

Deselect

4.75 to 5.5 V

4.5 to 5.5 V

3.0 to 3.6 V

VIH

High Z

Standby

WRITE

VIL

XVIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

(1)(1)

See Table 13 on page 24 for details.

High Z

CMOS standby

Deselect

≤ VSO(1)

High Z

Battery back-up

mode

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