| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
M95320-W bảng dữ liệu(PDF) 13 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
M95320-W bảng dữ liệu(HTML) 13 Page - STMicroelectronics |
|
13 / 44 page ![]() M95320, M95320-W, M95320-R Operating features Doc ID 5711 Rev 12 13/44 4.1.4 Power-down During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10), the device must be: ● deselected (Chip Select S should be allowed to follow the voltage applied on VCC) ● in Standby Power mode (there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes ICC, as specified in Table 13 to Table 16. When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1. 4.2.1 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as Serial Clock (C) already being low (as shown in Figure 5). The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low. Figure 5 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. Figure 5. Hold condition activation AI02029D HOLD C Hold Condition Hold Condition |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |