MB90583C datasheet(19/112 Pages) FUJITSU

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MB90580C Series

DS07-13710-7E

■ HANDLING DEVICES

Preventing Latch-up

CMOS ICs may cause Latch-up in the following situations:

• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.

• When a voltage exceeding the rating is applied between Vcc and Vss.

• When AVcc power is supplied prior to the Vcc voltage.

If Latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the

device. Use meticulous care not to let it occur.

For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply

voltage.

Handling unused input pins

Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused

input pins should be pulled up or pulled down through at least 2 k

Ω resistance.

Unused input/output pins may be left open in output state, but if such pins are in input state they should be

handled in the same way as input pins.

Treatment of the TX and RX pins with the IEBusTM unused

When the IEBus is not used, connect a pull-down resistor to the TX pin and a pull-down/pull-up resistor to the

RX pin.

Use of the external clock

When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration

below).

Power Supply Pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to

avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to

lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in

the ground level, and to conform to the total current rating.

Make sure to connect VCC and VSS pins via lowest impedance to power lines.

MB90580C series

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