MB90F474LPF datasheet(30/118 Pages) FUJITSU

30 / 118 page

MB90470 Series

(Continued)

: Interrupt request flag cleared by the interrupt clear signal. The stop request is available.

: Interrupt request flag cleared by the interrupt clear signal.

× : Interrupt request flag not cleared by the interrupt clear signal.

* : Note that flash write/erase cannot be used at the same time as the time base timer or watch timer.

Note :

• If two or more interrupt sources have the same interrupt number, the resource will clear both interrupt

request flags at the EI2OS/DMAC interrupt clear signal. Thus when EI2OS/

µDMA function of two sources

is used, the other interrupt function cannot be used. The interrupt request enable bit of the corresponding

resource should be set to “0” for software polling processing.

• Maximum assured operation frequency of µDMA is 16 MHz.

Interrupt source

EI2OS

support

µµµµDMA

channel no.

Interrupt vector

Interrupt control

No.

Address

No.

Address

SIO1

#37

FFFF68H

ICR13

0000BDH

SIO2

#38

FFFF64H

I2C interface

××

#39

FFFF60H

ICR14

0000BEH

A/D

#40

FFFF5CH

Flash write/erase, time base timer,

watch timer*

××

#41

FFFF58H

ICR15

0000BFH

Delay interrupt generator module

××

#42

FFFF54H

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