EPCS64 datasheet(16/38 Pages) ALTERA

16 / 38 page

3–16

Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

Serial Configuration Device Memory Access

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

Write Disable Operation

The write disable operation code is b'0000 0100, with the MSB listed first. The

write disable operation resets the write enable latch bit, which is bit 1 in the status

latch bit is automatically reset when implementing the write disable operation as well

as under the following conditions:

■

Power up

■

Write bytes operation completion

■

Write status operation completion

■

Erase bulk operation completion

■

Erase sector operation completion

Figure 3–6 shows the timing diagram for the write disable operation.

Read Status Operation

The read status operation code is b'0000 0101, with the MSB listed first. You can

use the read status operation to read the status register. Figure 3–7 and Figure 3–8

show the status bits in the status register of the serial configuration devices.

Setting the write in progress bit to 1 indicates that the serial configuration device is

busy with a write or erase cycle. Resetting the write in progress bit to 0 means no

write or erase cycle is in progress.

Figure 3–6. Write Disable Operation Timing Diagram

Figure 3–7. EPCS4, EPCS16, EPCS64, and EPCS128 Status Register Status Bits

Figure 3–8. EPCS1 Status Register Status Bits

nCS

DCLK

ASDI

DATA

01234567

Operation Code

High Impedance

Bit 7

Bit 0

Block Protect Bits [2..0]

Write In

Progress Bit

Write Enable

Latch Bit

BP2

BP1

BP0

WEL

WIP

Bit 7

Bit 0

Block Protect

Bits [1..0]

Write In

Progress Bit

Write Enable

Latch Bit

BP1

BP0

WEL

WIP

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