EP3C5 datasheet(22/34 Pages) ALTERA

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Chapter 1: Cyclone III Device Data Sheet

Switching Characteristics

Cyclone III Device Handbook, Volume 2

Altera Corporation

TCCS

—

200

—

200

—

200

Output jitter

(peak to peak)

—

500—

550

LOCK (2)

——

—

Notes to Table 1–30:

(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.

(2) tLOCK is the time required for the PLL to lock from the end of device configuration.

Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications (Note 1)

Symbol

Modes

C7, I7

C8, A7

Unit

Min

Max

Min

Max

Min

Max

HSC LK (input clock

frequency)

×10

437.5

370

320

MHz

×8

437.5

370

320

MHz

×7

437.5

370

320

MHz

×4

437.5

370

320

MHz

×2

437.5

370

320

MHz

×1

437.5

402.5

MHz

HSIODR

×10

100

875

100

740

100

640

Mbps

×8

875

740

640

Mbps

×7

875

740

640

Mbps

×4

875

740

640

Mbps

×2

875

740

640

Mbps

×1

437.5

402.5

Mbps

—

400—

400ps

Input jitter

tolerance

—

500—

550ps

LOCK (2)

——

—

Notes to Table 1–31:

(1) LVDS receiver is supported at all banks.

(2) tLOCK is the time required for the PLL to lock from the end of device configuration.

Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (Note 1) (Part 2

of 2)

Symbol

Modes

C7, I7

C8, A7

Unit

MinMax

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