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NB3N502DEVB bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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NB3N502DEVB bảng dữ liệu(HTML) 1 Page - ON Semiconductor |
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1 / 7 page ![]() © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 0 1 Publication Order Number: NB3N502DEVB/D NB3N502DEVB NB3N502 Evaluation Board User’s Manual Description The NB3N502 Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of the NB3N502 PLL Clock Multiplier. This user’s manual provides detailed information on the board’s contents, layout and use, and it should be used in conjunction with the NB3N502 data sheet which contains full technical details on device specifications and operation (www.onsemi.com). Board Features • Fully Assembled Evaluation Board • Accommodates the Electrical Characterization of the NB3N502 in the SOIC−8 Package • Supports the Use of a 5 MHz to 27 MHz Through−hole or Surface Mount Crystal • SMA Connectors are Provided for Auxiliary Input and Output Interfaces • Incorporates Onboard Slide Switch Controlled Multiplier Select Pins, Minimizing Excess Cabling This Evaluation Board Manual Contains • Information on the NB3N502 Evaluation Board • Appropriate Lab Setup • Evaluation Board Layout • Bill of Materials Figure 1. NB3N502 Evaluation Board http://onsemi.com |
Số phần tương tự - NB3N502DEVB |
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Mô tả tương tự - NB3N502DEVB |
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