M16CSLASH5M datasheet(21/159 Pages) RENESAS

21 / 159 page

REJ03B0267-0101

Rev.1.01

Page 21 of 156

Jul 23, 2010

M16C/5M Group, M16C/57 Group

1. Overview

Figure 1.8

Pin Assignments for 64-Pin Package (Top View)

Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual

pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.

P9_2 / AN3_2 / TB2IN / CRX0 (1)

P7_7 / TA3IN / CRX1 (1)

P7_6 / TA3OUT / CTX1 (1)

P9_3 / AN2_4 /CTX0 (1)

AVCC

VREF

P10_0 / AN_0

AVSS

P10_1 / AN_1

P10_2 / AN_2

P10_3 / AN_3

P10_4 / AN_4 / KI0

P10_5 / AN_5 / KI1

P10_6 / AN_6 / KI2

P10_7 / AN_7 / KI3

P0_0 / AN0_0

P0_1 / AN0_1

P0_2 / AN0_2

P7_5 / TA2IN / W / LIN0IN

P7_4 / TA2OUT / W / LIN0OUT

P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1

P7_2 / CLK2 / TA1OUT / V / RXD1

P7_1 / RXD2 / SCL2 / TA0IN / CLK1

P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1

P6_7 / TXD1

P6_6 / RXD1

P6_5 / CLK1

P6_4 / RTS1 / CTS1

P3_3 / CTS3 / RTS3 / SCS0

P3_2 / TXD3 / SSO0

P3_1 / RXD3 / SSI0

P3_0 / CLK3 / SSCK0

Note:

1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.

PLQP0064KB-A

(64P6Q-A)

(Top view)

M16C/5M Group

M16C/57 Group

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