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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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FM3104 bảng dữ liệu(PDF) 21 Page - Ramtron International Corporation |
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FM3104 bảng dữ liệu(HTML) 21 Page - Ramtron International Corporation |
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21 / 25 page  FM3104/16/64/256 Rev. 3.2 July 2010 Page 21 of 25 DC Operating Conditions, continued (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes RIN Input Resistance (pulldown) A1-A0 for VIN = VIL max A1-A0 for VIN = VIH min 20 1 K Ω M Ω VPFI Power Fail Input Reference Voltage 1.175 1.20 1.225 V VHYS Power Fail Input (PFI) Hysteresis (Rising) - 100 mV Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. All inputs at VSS or VDD, static. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to A0, A1, PFI, or /RST pins. 4. VBAK = 3.0V, VDD < 2.4V, oscillator running, CNT1-2 at VBAK. 5. /RST is asserted low when VDD < VTP. 6. The minimum VDD to guarantee the level of /RST remains a valid VOL level. 7. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified. 8. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM31xx. 9. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 10. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max. AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 250 100 100 ns tR Input Rise Time 1000 300 300 ns 1 tF Input Fall Time 300 300 100 ns 1 tSU:STO Stop Condition Setup Time 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns All SCL specifications as well as start and stop conditions apply to both read and write operations. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V) Symbol Parameter Typ Max Units Notes CIO Input/Output Capacitance - 8 pF 1 CXTAL X1, X2 Crystal pin Capacitance 12 - pF 1, 2 Notes 1 This parameter is characterized but not tested. 2 The crystal attached to the X1/X2 pins must be rated as 6pF. Data Retention (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V) Parameter Min Units Notes Data Retention 10 Years |
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