SST25LF080A datasheet(7/25 Pages) SST

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EOL Product Data Sheet

8 Mbit SPI Serial Flash

SST25LF080A

S71248-06-EOL

1/06

Block Protection (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of the

memory area, as defined in Table 5, to be software pro-

tected against any memory Write (Program or Erase)

operations. The Write-Status-Register (WRSR) instruction

is used to program the BP1 and BP0 bits as long as WP#

is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase

can only be executed if Block-Protection bits are both 0.

After power-up, BP1 and BP0 are set to 1.

Block Protection Lock-Down (BPL)

WP# pin driven low (VIL), enables the Block-Protection-

Lock-Down (BPL) bit. When BPL is set to 1, it prevents any

further alteration of the BPL, BP1, and BP0 bits. When the

WP# pin is driven high (VIH), the BPL bit has no effect and

its value is “Don’t Care”. After power-up, the BPL bit is

reset to 0.

Auto Address Increment (AAI)

The Auto Address Increment Programming-Status bit pro-

vides status on whether the device is in AAI programming

mode or Byte-Program mode. The default at power up is

Byte-Program mode.

TABLE

5: SOFTWARE STATUS REGISTER BLOCK PROTECTION1

1. Default at power-up for BP1 and BP0 is ‘11’.

Protection Level

Status

Bit

Protected Memory Area

BP1

BP0

8 Mbit

None

1 (1/4 Memory Array)

0C0000H-0FFFFFH

2 (1/2 Memory Array)

080000H-0FFFFFH

3 (Full Memory Array)

000000H-0FFFFFH

T5.0 1248

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