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PIC16F720-E/ML bảng dữ liệu(PDF) 170 Page - Microchip Technology |
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PIC16F720-E/ML bảng dữ liệu(HTML) 170 Page - Microchip Technology |
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170 / 244 page ![]() PIC16F/LF720/721 DS41430A-page 170 2010 Microchip Technology Inc. 19.2 Wake-up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. FIGURE 19-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Oscillator CLKOUT(3) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC - 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(2) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h) Dummy Cycle PC + 2 0004h 0005h Dummy Cycle TOST(1) PC + 2 Note 1: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC mode. 2: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 3: CLKOUT is not available in EC Oscillator mode, but shown here for timing reference. TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ---- INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. |
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