MRF24J40-ISLASHT datasheet(7/156 Pages) MICROCHIP

7 / 156 page

Preliminary

DS39776C-page 7

MRF24J40

2.0

HARDWARE DESCRIPTION

2.1

2.1 Overview

The MRF24J40 is an IEEE 802.15.4 Standard

compliant 2.4 GHz RF transceiver. It integrates the

PHY and MAC functionality in a single chip solution.

Figure 2-1 is a block diagram of the MRF24J40

circuitry.

A frequency synthesizer is clocked by an external

20 MHz crystal and generates a 2.4 GHz RF frequency.

The receiver is a low-IF architecture consisting of a Low

Noise Amplifier (LNA), down conversion mixers, poly-

phase channel filters and baseband limiting amplifiers

with a Receiver Signal Strength Indicator (RSSI).

The transmitter is a direct conversion architecture with

a 0 dBm maximum output (typical) and 36 dB power

control range.

An internal Transmit/Receive (TR) switch combines the

transmitter and receiver circuits into differential RFP

and RFN pins. These pins are connected to impedance

matching circuitry (balun) and antenna. An external

Power Amplifier (PA) and/or LNA can be controlled via

the GPIO pins.

Six General Purpose Input/Output (GPIO) pins can be

configured for control or monitoring purposes. They

can also be configured to control external PA/LNA RF

switches.

The power management circuitry consists of an

integrated Low Dropout (LDO) voltage regulator. The

MRF24J40 can be placed into a very low-current (2

μA

typical) Sleep mode. An internal 100 kHz oscillator or

32 kHz external crystal oscillator can be used for Sleep

mode timing.

The Media Access Controller (MAC) circuitry verifies

reception and formats for transmission IEEE 802.15.4

Standard compliant packets. Data is buffered in Trans-

mit and Receive FIFOs. Carrier Sense Multiple

Access-Collision Avoidance (CSMA-CA), superframe

constructor, receive frame filter and security engine

functionality are implemented in hardware. The

security engine provides hardware circuitry for

AES-128 with CTR, CCM and CBC-MAC modes.

Control of the transceiver is via a 4-wire SPI, interrupt,

wake and Reset pins.

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