R5F2M110ADSP datasheet(11/48 Pages) RENESAS

11 / 48 page

R8C/M11A Group, R8C/M12A Group

2. Central Processing Unit (CPU)

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0010EJ0010 Rev.0.10

Page 11 of 45

Aug 25, 2010

Central Processing Unit (CPU)

Figure 2.1 shows the 13 CPU Registers. The registers, R0, R1, R2, R3, A0, A1, and FB form a single register bank.

The CPU has two register banks.

Figure 2.1

CPU Registers

The higher 4 bits of INTB are INTBH and

the lower 16 bits of INTB are INTBL.

Interrupt table register

Data registers (1)

Address registers (1)

Frame base register (1)

User stack pointer

Interrupt stack pointer

Static base register

Program counter

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bits

Processor interrupt priority level

Reserved bit

Note:

1. These registers form a single register bank.

The CPU has two register banks.

Flag register

b31

b15

R0H (R0 high-order byte)

R1H (R0 high-order byte)

R0L (R1 low-order byte)

R1L (R1 low-order byte)

INTBH

b19

INTBL

b15

b19

b15

USP

ISP

b15

FLG

b15

IPL

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