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PT8300 V1.8

- 16 -

February, 2006

16-Bit I/O Expander IC

PT8300

Notes:

1. Dimensioning and tolerancing per ANSI Y14.5-1982.

2. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and

gate burrs shall not exceed 0.15mm (0.006 in) per side.

3. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusion shall not

exceed 0.15mm (0.016in) per side.

4. The chamfer on the body is optional. If it is not present, a visual index feature must be located

within the crosshatched area.

5. L is the length of terminal for soldering to a substrate.

6. N is the number of terminal positions (N=28).

7. The lead width B as measured 0.36mm (0.014in) or greater above the seating plane, shall not

exceed a maximum value of 0.61 mm (0.024 in).

8. Controlling dimension: MILLIMETER

9. Refer to JEDEC MS-013 Variation AE.

JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION