AT90PWM81 datasheet(39/325 Pages) ATMEL

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7734P–AVR–08/10

AT90PWM81

5.5.2

CLKPR – Clock Prescaler Register

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is

only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by

hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit

within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the AT90PWM81 and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock.

These bits can be written run-time to vary the clock frequency to suit the application requirements. As the

divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced

when a division factor is used. The division factors are given in Table 5-10.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change

the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to

zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting in order not to disturb the procedure.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the

CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a

division factor of eight at start up. This feature should be used if the selected clock source has a higher fre-

quency than the maximum frequency of the device at the present operating conditions. Note that any value

can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must

ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than

the maximum frequency of the device at the present operating conditions. The device is shipped with the

CKDIV8 Fuse programmed.

Bit

3210

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

Table 5-10.

Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

128

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