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20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

Figure 5. SPI Command Byte

Figure 6. SPI Register Access Write

Serial-Digital Interface

The MAX11206/MAX11207 interface is fully compatible

with SPI-, QSPI-, and MICROWIRE-standard serial inter-

faces. The SPI interface provides access to nine on-chip

registers that are 8 or 24 bits wide.

Drive CS low to transfer data in and out of the devices.

Clock in data at DIN on the rising edge of SCLK. The

RDY/DOUT output serves two functions: conversion sta-

tus and data read. To find the conversion status, assert

CS low and read the RDY/DOUT output; the conversion

is in progress if the RDY/DOUT output reads logic-high

and the conversion is complete if the RDY/DOUT output

reads logic-low. Data at RDY/DOUT changes on the

falling edge of SCLK and is valid on the rising edge of

SCLK. DIN and DOUT are transferred MSB first. Drive

CS high to force DOUT high impedance and cause

the devices to ignore any signals on SCLK and DIN.

Connect CS low for 3-wire operation. Figures 5, 6, and 7

show the SPI timing diagrams.

HIGH-Z

HIGH-Z

SCLK

0

X

1

1

0

CAL1

CAL0

IMPD

RATE2

RATE1

RATE0

8

DIN

CS

RDY/DOUT

HIGH-Z

HIGH-Z

SCLK

0

X

1

1

1

X

RS3

RS2

RS1

RS0

W/R

D7

D6

D5

D4

D3

D2

D1

D0

16

8

9

DIN

CS

RDY/DOUT

SPI REGISTER ACCESS WRITE