AD9963-EBZ datasheet(28/60 Pages) AD

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AD9961/AD9963

Rev. 0 | Page 28 of 60

Address

Bit(s)

Parameter

Function

Rx Data Interface

0x3F

Unused

RX_CLK

0: when SINGLERX is active, use Q side clock.

1: when SINGLERX is active, use I side clock.

RX_BUS

0: when SINGLERX is active, use the Q ADC.

1: when SINGLERX is active, use the I ADC.

SINGLERX

0: use both Rx paths.

1: use only one Rx path.

TXCLK_MD

This bit controls the operation of the TXCLK pin when the chip is

configured in half-duplex 1-clock mode. This bit is otherwise ignored.

0: the TXCLK pin is set to a high impedance output.

1: the DLL clock output is driven onto the TXCLK pin.

HD_BUSCTL

0: selects SPI mode to control bus direction in half-duplex mode.

1: selects Pin mode to control bus direction in half-duplex mode.

SPI bit to set Tx or Rx is Register 0x30, Bit 0. Register 0x30, Bit 1 is ignored

in this case.

HD_CLKMD

0: selects 1-clock submode if in half-duplex mode.

1: selects 2-clock submode if in half-duplex mode.

FULL_DUPLEX

0: configures the digital interface for half-duplex mode (covers both 1-

clock and 2-clock submodes).

1: configures the digital interface for full-duplex mode.

DAC12 Config

0x40

DAC12B_EN

0: powers down DAC12B.

1: enables DAC12B.

DAC12A_EN

0: powers down DAC12A.

1: enables DAC12A.

DAC12B_TOP

0: sets DAC12B range to 3.3 × V

AUXDACREF.

1: sets DAC12B range to 1.8 × V

AUXDACREF.

DAC12A_TOP

0: sets DAC12A range to 3.3 × V

AUXACREF.

1: sets DAC12A range to 1.8 × V

AUXDACREF.

3:2

Unused

AUXDAC_REF

Selects where the voltage reference for all of the auxiliary DACs is

derived.

0: resistive divider from AUX33V. V

AUXDACREF = VAUX33V /3.3.

1: selects the 1.0 V bandgap voltage. V

AUXDACREF = 1.0 V.

DAC_UPDATE

This bit determines which of the two data words updates all four of the

auxiliary DACs.

0: update DACs after LSB write.

1: update DACs after MSB write.

DAC12A MSBs

0x41

7:0

DAC12A[11:4]

DAC12A voltage control word (upper eight bits).

DAC12A LSBs

0x42

7:4

Unused

3:0

DAC12A[3:0]

DAC12A voltage control word (lower four bits).

DAC12B MSBs

0x43

7:0

DAC12B[11:4]

DAC12B voltage control word (upper eight bits).

DAC12B LSBs

0x44

7:4

Unused

3:0

DAC12B[3:0]

DAC12B voltage control word (lower four bits).

DAC10B Config

0x45

DAC10B_EN

0: powers down DAC10B.

1: enables DAC10B.

6:5

Unused

4:2

DAC10B_TOP[2:0]

Sets the DAC output voltage at the top range as follows:

000: 1.0 V.

001: 1.5 V.

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