AD9125 datasheet(21/56 Pages) AD

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AD9125

Rev. 0 | Page 21 of

Addr

(Hex)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Compare

Q1 MSBs

0x6F

Compare Value Q1[15:8]

0xAA

SED I LSBs

0x70

Errors detected I_BITS[7:0]

0x00

SED I MSBs

0x71

Errors detected I_BITS[15:8]

0x00

SED Q LSBs

0x72

Errors detected Q_BITS[7:0]

0x00

SED Q MSBs

0x73

Errors detected Q_BITS[15:8]

0x00

Die Revsion

0x7F

Revision[3:0]

0x0C

DEVICE CONFIGURATION REGISTER DESCRIPTIONS

Table 11. Device Configuration Register Descriptions

Name

Address

(Hex)

Bits

Name

Description

Default

Comm

0x00

SDIO

SDIO operation.

0 = SDIO operates as an input only.

1 = SDIO operates as a bidirectional input/output.

LSB_FIRST

Serial port communication LSB or MSB first.

0 = MSB first.

1 = LSB first.

Reset

1 = device is held in reset when this bit is written high

and is held there until the bit is written low.

Power Control

0x01

Power-down DAC I

1 = powers down DAC I.

Power-down DAC Q

1 = powers down DAC Q.

Power-down data

receiver

1 = powers down the input data receiver.

Power-down auxiliary

ADC

1 = powers down the auxiliary ADC for temperature

sensor.

PLL lock status

1 = PLL is locked.

Data Format

0x03

Binary data format

0 = input data is in twos complement format.

1 = input data is in binary format.

Q data first

Indicates I/Q data pairing on data input.

0 = I data sent to data receiver first.

1 = Q data sent to data receiver first.

MSB swap

Swaps the bit order of the data input port.

0 = order of the data bits corresponds to the pin

descriptions.

1 = bit designations are swapped; most significant bits

become the least significant bits.

[1:0]

Data bus width

Data receiver interface mode.

00 = dual-word mode; 32-bit interface bus width.

01 = word mode; 16-bit interleaved interface bus width.

10 = byte mode; 8-bit interleaved interface bus width.

11 = invalid.

See the CMOS Input Data Ports section for details on

the operation of the different interface modes.

Interrupt Enable 1

0x04

Enable PLL lock lost

1 = enables interrupt for PLL lock lost.

Enable PLL lock

1 = enables interrupt for PLL lock.

Enable sync signal lost

1 = enables interrupt for sync signal lock lost.

Enable sync signal lock

1 = enables interrupt for sync signal lock.

Enable sync phase

locked

1 = enables interrupt for clock generation ready.

Enable soft FIFO sync

1 = enables interrupt for soft FIFO reset.

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