KM416RD8ACD-RK70 datasheet(39/64 Pages) SAMSUNG

39 / 64 page

Page 36

KM416RD8AC(D)/KM418RD8AC(D)

Direct RDRAM™

Rev. 1.01 Oct. 1999

Figure 39: TPARM Register

15 14 13 12 11 10

TCDLY0

TCLS

TCAS

Read/write register.

Reset value is undefined.

TCAS1..0 - Specifies the tCAS-C core parameter in

tCYCLE units. This should be “10” (2•tCYCLE).

TCLS1..0 - Specifies the tCLS-C core parameter in

tCYCLE units. Should be “10” (2•tCYCLE).

TCDLY0 - Specifies the tCDLY0-C core parameter in

tCYCLE units. This adds a programmable delay to Q

(read data) packets, permitting round trip read delay to

all devices to be equalized. This field may be written

with the values “011” (3

•t

CYCLE) through “101”

•t

CYCLE).

Control Register: TPARM

Address: 04816

The equations relating the core parameters to the

datasheet parameters follow:

tCAS-C = 2•tCYCLE

tCLS-C = 2•tCYCLE

tCPS-C = 1•tCYCLE

Not programmable

tOFFP = tCPS-C + tCAS-C + tCLS-C - 1•tCYCLE

= 4

•t

CYCLE

tRCD = tRCD-C + 1•tCYCLE - tCLS-C

= tRCD-C - 1•tCYCLE

tCAC = 3•tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C

(see table below for programming ranges)

011

101

100

TCDLY0

011

3•t CYCLE

5•t CYCLE

4•t CYCLE

tCDLY0-C

3•t CYCLE

010

001

010

TCDLY1

000

•t

CYCLE

•t

CYCLE

•t

CYCLE

•t

CYCLE

tCDLY1-C

•t

CYCLE

•t

CYCLE

•t

CYCLE

•t

CYCLE

•t

CYCLE

tCAC

•t

CYCLE

Figure 40: TFRM Register

15 14 13 12 11 10

TFRM3..0

Read/write register.

Reset value is undefined.

TFRM3..0 - Specifies the position of the framing point

in tCYCLE units. This value must be greater than or

equal to the tFRM,MIN parameter. This is the minimum

offset between a ROW packet (which places a device at

ATTN) and the first COL packet (directed to that

device) which must be framed. This field may be

written with the values “0111” (7

•t

CYCLE) through

“1010” (10

•t

CYCLE). TFRM is usually set to the value

which matches the largest tRCD,MIN parameter (modulo

•t

CYCLE) that is present in an RDRAM in the memory

system. Thus, if an RDRAM with tRCD,MIN =

•t

CYCLE were present, then TFRM would be

programmed to 9

•t

CYCLE.

Control Register: TFRM

Address: 04916

Figure 41: TRDLY Register

15 14 13 12 11 10

TCDLY1

Read/write register.

Reset value is undefined.

TCDLY1 - Specifies the value of the tCDLY1-C core

parameter in tCYCLE units. This adds a programmable

delay to Q (read data) packets, permitting round trip

read delay to all devices to be equalized. This field may

be written with the values “000” (0

•t

CYCLE) through

“010” (2

•t

CYCLE). Refer to Figure 39 for more details.

Control Register: TCDLY1

Address: 04a16

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