SA3488 datasheet(8/20 Pages) SAMES

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SA3488

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PIN DESCRIPTION

Designation

Description

Bidirectional data bus used to transfer data and instructions

to and from the microprocessor. The output bus is 8 bits

wide and the input 5 bits wide. D0 is the least significant

digit. The bus is tristate and is not available for use while

RESET is held low.

C/D

In a write operation C/D = 0 qualifies bus content as data,

while C/D = 1 qualifies it as a opcode. In a read operation

C/D = 0 selects OR1 whereas C/D = 1 selects OR2.

CS2

Chip select pins. Enable the device to perform valid read

CS1

and write operations (active low). The two pins allow for

row column selection for different types of microprocessors;

normally though one is tied low.

Address select or match pins. With S1 and S2 hardwired

to ground or V

CC, signals on A1 and A2 give rise to a 28S1

matched or unmatched condition i.e. S1=A1, S2=A2 =>a

matched condition. Since in a matrix structure, devices in

the same row share the same PCM output bus, instructions

pertaining to channel connections (matched condition),

must be processed as channel disconnections in the other

devices (unmatched condition).

Two channels can

therefore never collide.

When CS1 and CS2 are low, WR enables data transfer

from the microprocessor to the device. Data, opcode and

control signals are latched on the rising edge of WR. To

ensure simultaneous instruction execution in a multichip

configuration the WR rising edge must be 20 to 20 + t

WL(CK)

nsec late relative to the clock falling edge.

When CS1 and CS2 are low and a matched condition

exists, a low level on RD enables OR1 or OR2 for a read

operation. In addition the rising edge of RD latches C/D

and the matched condition pins in order to direct the

internal

flow of operations. In a multichip configuration

the same timing requirement must be met as in the WR

case.

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