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SC493 bảng dữ liệu(PDF) 19 Page - Semtech Corporation |
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SC493 bảng dữ liệu(HTML) 19 Page - Semtech Corporation |
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19 / 28 page ![]() SC493 19 Applications Information (continued) L OUT IN INJ R V V I The following describes one way to design the virtual ESR circuit. 2 1 2 1 SW C L R R R R f 2 1 C C The current through resistance R L will all go through CL and the voltage change through capacitor C L will be shown by the next equation. L ON L OUT IN INJ C t R V V V All of this voltage will be coupled into the FB pin if the rules previously stated are followed. Note that the output ripple voltage has not been taken into account. The output voltage ripple will also be coupled through the C L and C C path into the FB pin. The ripple voltage at the output due to the output capacitance (ignoring the capacitance ESR) is shown by the next equation. SW OUT RIPPLE RIPPLE _ COUT f C 8 I V The ripple due to the capacitance ESR alone is shown by the next equation. V ESR_RIPPLE = IRIPPLE x RESR The output ripple voltage due to output capacitance has a 90° phase lag with respect to the ripple voltage gener- ated by the virtual ESR. The actual ripple voltage seen at the FB pin (VFB_RIPPLE) can be approximated by the next equation. 2 RIPPLE _ COUT 2 RIPPLE _ ESR INJ RIPPLE _ FB V ) V V ( V Resistor Divider Selection The DC voltage at the FB pin is shown by the next equation. 2 V V 5 . 0 V RIPPLE _ FB FB The resistor divider value should be selected using the next equation. 2 2 1 FB OUT R R R V V |
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