SSTVF16859_05 datasheet(7/23 Pages) PHILIPS

7 / 23 page

9397 750 15157

Product data sheet

Rev. 02 — 19 July 2005

7 of 23

Philips Semiconductors

SSTVF16859

13-bit 1 : 2 SSTL_2 registered buffer for DDR

Functional description

Refer to Figure 1 “Logic diagram of SSTVF16859”.

7.1 Function table

[1]

Q0 is the previous state of output Qn.

Data input. Clocked in on the crossing of the rising

edge of CK and the falling edge of CK.

D10

D11

D12

D13

VREF

input reference voltage

positive master clock input

negative master clock input

RESET

Asynchronous reset input. Resets registers and

disables data and clock differential input receivers.

n.c.

A1, A2, A3, A4,

A5, A6, B5, B6,

C5, C6, H5, J5,

K5, K6, P5, P6,

R1, R2, R3, R4,

R5, R6, T1, T2,

T3, T4, T5, T6

not connected

Table 3:

Pin description …continued

Symbol

Description

TSSOP64

HVQFN56

LFBGA96

Table 4:

Function selection (each ﬂip-ﬂop)

H = HIGH voltage level; L = LOW voltage level;

↓ = HIGH-to-LOW transition;

↑ = LOW-to-HIGH transition; X = Don’t care

Inputs

Output

RESET

↑

↓

↑

↓

L or H

Q0 [1]

X or ﬂoating

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