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CDCE906PW bảng dữ liệu(PDF) 21 Page - Texas Instruments |
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CDCE906PW bảng dữ liệu(HTML) 21 Page - Texas Instruments |
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21 / 42 page ![]() www.ti.com FUNCTIONAL DESCRIPTION Zero ppm Audio and Video System Clock Generation and Divider Setting CDCE906 SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007 The CDCE906 is ideally suited for audio and video applications. It consists of a triple PLL clock generator which generates up to six audio, video and system clocks from i.e. a 27-MHz master clock. The output frequencies are programmable to meet different application requirements. The master clock can be either a crystal oscillator or an external input clock signal. The CDCE906 provides a very low jitter, high accuracy clock with zero ppm for the common audio and video clocks. The following table shows the system clocks versus the standard sampling frequency and the corresponding divider settings. Divider Divider Audio Rate fs x 256 fs x 384 Error ppm Error ppm [kHz] [MHz] [MHz] M N P M N P 16 4.096 375 2048 36 0 6.144 125 768 27 0 22.05 5.6448 75 392 25 0 8.4672 125 588 15 0 24 6.144 125 768 27 0 9.216 125 768 18 0 32 8.192 375 2048 18 0 12.288 375 2048 12 0 44.1 11.2896 375 1568 10 0 16.9344 125 784 10 0 48 12.288 375 2048 12 0 18.432 125 768 9 0 96 24.576 375 2048 6 0 36.864 375 2048 4 0 Divider Divider Audio Rate fs x 512 fs x 768 Error ppm Error ppm [kHz] [MHz] [MHz] M N P M N P 16 8.192 375 2048 18 0 12.288 375 2048 12 0 22.05 11.2896 375 1568 10 0 16.9344 125 784 10 0 24 12.288 375 2048 12 0 18.432 125 768 9 0 32 16.384 375 2048 9 0 24.576 375 2048 6 0 44.1 22.5792 375 1568 5 0 33.8688 125 784 5 0 48 24.576 375 2048 6 0 36.864 375 2048 4 0 96 49.152 375 2048 3 0 73.728 375 2048 2 0 NOTE: Input frequency is 27 MHz. Video Divider Divider Divider 2 Error 1 Error 0.5 Error Rate [MHz] ppm [MHz] ppm [MHz] ppm M N P M N P M N P [MHz] 27 54 1 8 4 0 27 - - 1 0 13.5 - - 2 0 Copyright © 2005–2007, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link(s): CDCE906 |
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