1.

General description

The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed for

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTU32864 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when

LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from

25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and undriven (floating) data, clock and

are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must

always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTU32864 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from

changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is

LOW, the Qn outputs will function normally. The RESET input has priority over the DCS

and CSR control and will force the outputs LOW. If the DCS-control functionality is not

desired, then the CSR input can be hardwired to ground, in which case the setup time

requirement for DCS would be the same as for the other Dn data inputs.

The SSTU32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)

package.

SSTU32864

1.8 V configurable registered buffer for DDR2 RDIMM

applications

Rev. 02 — 22 October 2004

Product data sheet