SC415_08 datasheet(13/30 Pages) SEMTECH

13 / 30 page

SC415

Applications Information (continued)

The resistor sensing circuit is shown in Figure 6 with RILIM

= R1 and RSENSE = R4

Figure 6

The following over-current equation can be used for

both RDSON or resistive sensing. For RDSON sensing, the

MOSFET RDSON rating is used for the value of RSENSE.

ILOC(Valley) = 10μA × RILIM / RSENSE

Power Good Output

Each output provides a power good (PGD) output, which

is an open-drain output requiring a pull-up resistor. When

the output voltage as sensed at FB is -9% from the 750mV

reference (682mV), PGD is pulled low. It is held low until

the output voltage returns above -9% of nominal; the

falling edge of PGD is not latched. PGD is held low during

start-up and will not be allowed to transition high until

soft-start is completed, when SS reaches 750mV. There

is a 5μs delay built into the PGD circuit to prevent false

transitions.

PGD also transitions low if the FB pin exceeds +20% of

nominal (900mV), which is also the over-voltage shutdown

point.

Output Over-Voltage Protection (OVP)

In steady state operation, when FB exceeds 20% of

nominal (900mV), DL latches high and the low-side

MOSFET is turned on. DL stays high and the SMPS stays

off until the EN/PSV input is toggled or VDD1 is recycled.

There is a 5μs delay built into the OVP detector to prevent

false transitions. PGD is also held low after an OVP.

Output Under-Voltage Protection (UVP)

When FB falls 30% below nominal (to 525mV) for eight

consecutive clock cycles, the output is shut off; the DL/

DH drivers are pulled low to tristate the MOSFETs, and the

converter stays off until its Enable input is toggled or the

VDD1 supply is recycled. The other output does not shut

off during UVP.

POR and UVLO

Under-voltage lockout circuitry (UVLO) inhibits switching

and tristates all DH/DL drivers until the +5V supply at

VDD1 rises above typically 4.1V. An internal power-on

reset (POR) occurs when VDD1 exceeds 4.1V, which resets

the fault latches and quickly discharges the soft-start

capacitors to prepare the PWM for startup switching. At

this time the SC415 will exit UVLO and begin the soft-start

cycle.

Startup Sequence

The startup sequence for each output relies on an external

ramp at the SS pin. During startup, the FB comparator

uses the SS ramp voltage as the reference until SS reaches

750mV, at which point the FB comparator switches over

to the internal fixed 750mV reference. The external ramp

is created by connecting a capacitor to the SS pin.

Before starting, with EN low, the SS pin is internally tied to

GND through 4kΩ. When EN is released, SS is briefly pulled

to GND through 16 ohms to discharge residual voltage on

the SS capacitor. Then the resistances are removed and a

5μA source current flows out of the SS pin.

Vout

+5V

PAD

VDDP

ILIM

BST

VIN

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