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CDCE706 bảng dữ liệu(PDF) 14 Page - Texas Instruments

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tên linh kiện CDCE706
Giải thích chi tiết về linh kiện  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER
PDF  40 Pages
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Trang chủ  http://www.ti.com
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CDCE706 bảng dữ liệu(HTML) 14 Page - Texas Instruments

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T0131-01
P
S
P
t
(BUS)
t
su(SDATA)
t
h(SDATA)
t
r(SDATA)
t
f(SDATA)
SCLK
SDATA
V
IH(SM)
V
IH(SM)
V
IL(SM)
V
IL(SM)
A
Bit7(MSB)
Bit6
Bit0(LSB)
t
su(START)
t
h(START)
t
w(SCLL)
t
w(SCLH)
t
r(SM)
t
su(STOP)
t
f(SM)
SMBus Hardware Interface
9
10
SDATA
SCLK
SMBHost
CDCE706
C
BUS
C
BUS
R
P
R
P
S0376-01
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com
Block-Read Programming Sequence
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
CommandCode
A
Sr
Slave Address
Rd
A
8
1
8
1
8
1
1
Byte Count N
A
Data Byte 0
A
- - - - -
Data Byte N – 1
NA
P
Figure 10. Block-Read Protocol
Figure 11. Timing Diagram, Serial Control Interface
Figure 12 shows how the CDCE706 clock synthesizer is connected to the SMBus. Note that the current through
the pullup resistors (Rp) must meet the SMBus specifications (minimum 100 µA, maximum 350 µA). If the
CDCE706 is not connected to the SMBus, the SDATA and SCLK inputs must be connected with 10-k
Ω resistors
to VCC to avoid floating input conditions.
Figure 12. SMBus Hardware Interface
14
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Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): CDCE706



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