EPC4 datasheet(19/34 Pages) ALTERA

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–19

Functional Description

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Programmable Configuration Clock

The configuration clock (DCLK) speed is user programmable. One of two clock sources

can be used to synthesize the configuration clock; a programmable oscillator or an

external clock input pin (EXCLK). The configuration clock frequency can be further

synthesized using the clock divider circuitry. This clock can be divided by the N

counter to generate your DCLK output. The N divider supports all integer dividers

between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock

divisions other than non-integer divisions is 50% (for the non-integer dividers, the

duty cycle will not be 50%). Refer to Figure 1–5 for a block diagram of the clock

divider unit.

The DCLK frequency is limited by the maximum DCLK frequency the FPGA supports.

f The maximum DCLK input frequency supported by the FGPA is specified in the

appropriate FPGA family chapter in the Configuration Handbook.

Table 1–6. Stratix Compression Ratios (Note 1)

Item

Minimum

Average

Logic Utilization

98%

64%

Compression Ratio

1.9

2.3

% Size Reduction

47%

57%

Note to Table 1–6:

(1) These numbers are preliminary. They are intended to serve as a guideline, not a specification.

Figure 1–5. Clock Divider Unit

Configuration Device

Clock Divider Unit

Divide

by N

External Clock

(Up to 100 MHz)

Internal Oscillator

10 MHz

33 MHz

50 MHz

66 MHz

DCLK

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