DLPC200 datasheet(32/41 Pages) TI

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DMD_DAT(14:0)

DMD_SCTRL

DMD_CLK

tp_clkper

tp_su

tp_wl

tp_wh

tp_h

SPI_CLK

SPI_DATA

tp_su

tp_h

tp_wh

tp_wl

tp_clkper

DLPC200

DLPS014A – APRIL 2010 – REVISED MAY 2010

www.ti.com

Figure 13. DMD I/F Timing

DAD Interface

The DLPC200 ASIC DAD interface consists of a 125 kMHz (nominal) serial communications port (SCP).

DAD INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

TYP

MAX

UNIT

fclock

Clock frequency

125

kHz

tp_clkper

Clock period

tp_wh

Pulse width low

tp_wl

Pulse width high

tp_su

SCPDI setup time

7.3

tp_h

SCPDI hold time

5.7

Figure 14. DAD I/F Timing

DDR2 SDR Memory Interface

The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is internally configured as a

multibank DRAM. The Controller DDR-2 Memory interface consists of four 32 Mbit by 16-bit wide, DDR-2

interface with double data rate signaling operating at 133.33MHz (nominal). A bidirectional data strobe (DQS,

DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe

transmitted by the DDR2 SDRAM during READ commands and by the memory controller during WRITE

commands. DQS is edge-aligned with data for READ commands and center-aligned with data for WRITE

commands.

The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK#

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