BQ76PL536PAP datasheet(2/58 Pages) TI

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DRDY

FAULT

ALERT

SPI

PACK-

PACK+

GPAI

GPIO

AUX

REG50

SPI

(North)

CONV

CBx (6)

CONTROL (North)

bq76PL536

CELL_1

CELL_6

GPAI

GPIO

AUX

SPI

(North)

CBx (6)

CONTROL (North)

bq76PL536

CELL_1

CELL_6

TONEXTDEVICE

CONTROL (South)

SPI

(South)

SouthInterface

(notusedonbottomdevice)

bq76PL536

SLUSA08A – DECEMBER 2009 – REVISED JULY 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The host microcontroller controls cell balancing of individual cells by setting the registers (via SPI) which control

the appropriate CBx outputs. These outputs can be turned off via the same control, or automatically by the

internal programmable safety timer. The balancing bypass current is set via an external series resistor and FET.

TYPICAL IMPLEMENTATION

Figure 1. Simplified System Connection

PIN DETAILS

PIN FUNCTIONS

TYPE(1)

DESCRIPTION

NO.

NAME

VC6

Sense voltage input terminal for the positive terminal of the sixth cell

CB6

Cell-balance control output

VC5

Sense voltage input terminal for the positive terminal of the fifth cell

CB5

Cell-balance control output

VC4

Sense voltage input terminal for the positive terminal of the fourth cell

CB4

Cell-balance control output

(1)

Key: I = digital input, AI = analog input, O = digital output, OD = open-drain output, T = 3-state output, P = power.

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