FS6370

Table 13: AC Timing Specifications (Continued)

Parameter

Symbol

Conditions/Description

Clock

(MHz)

Min.

Typ.

Max.

Units

Clock Output (PLL C clock via CLK_C pin)

Duty Cycle*

Ratio of pulse width (as measured from rising edge to next falling

edge at 2.5V) to one clock period

100

45

55

%

On rising edges 500µs apart at 2.5V relative to an ideal clock,

active

100

45

Jitter, Long Term (

σ

On rising edges 500µs apart at 2.5V relative to an ideal clock,

active (A=50MHz, B=60MHz, D=14.318MHz)

40

105

ps

100

120

Jitter, Period (peak-peak)*

(A=50MHz, B=60MHz, D=14.318MHz)

40

440

ps

Clock Output (Crystal Oscillator via CLK_D pin)

Duty Cycle*

Ratio of pulse width (as measured from rising edge to next falling

edge at 2.5V) to one clock period

14.318

45

55

%

On rising edges 500µs apart at 2.5V relative to an ideal clock,

active

14.318

20

Jitter, Long Term (

σ

C=40MHz)

14.318

40

ps

14.318

90

Jitter, Period (peak-peak)*

C=40MHz)

14.318

450

ps

are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical.

Table 14: Serial Interface Timing Specifications

Parameter

Symbol

Conditions/Description

Min.

Max.

Units

Clock frequency

SCL

0

100

kHz

Bus free time between STOP and START

4.7

μs

Set up time, START (repeated)

4.7

μs

Hold time, START

4.0

μs

Set up time, data input

SDA

250

ns

Hold time, data input

SDA

0

μs

Output data valid from clock

Minimum delay to bridge undefined region of the falling

edge of SCL to avoid unintended START or STOP

3.5

μs

Rise time, data and clock

SDA, SCL

1000

ns

Fall time, data and clock

SDA, SCL

300

ns

High time, clock

SCL

4.0

μs

Low time, clock

SCL

4.7

μs

Set up time, STOP

4.0

μs

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