PC912XDP512F0CALR datasheet(167/1348 Pages) FREESCALE

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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

167

5.3.2.2

ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence but will not start a new sequence.

Read: Anytime

Write: Anytime

76543210

ETRIGSEL

0000

ETRIGCH2

ETRIGCH1

ETRIGCH0

Reset

00000111

= Unimplemented or Reserved

Figure 5-4. ATD Control Register 1 (ATDCTL1)

Table 5-3. ATDCTL1 Field Descriptions

Field

Description

ETRIGSEL

External Trigger Source Select — This bit selects the external trigger source to be either one of the AD

channels or one of the ETRIG3–0 inputs. See the device overview chapter for availability and connectivity of

ETRIG3–0 inputs. If ETRIG3–0 input option is not available, writing a 1 to ETRISEL only sets the bit but has

not effect, that means still one of the AD channels (selected by ETRIGCH2–0) is the source for external trigger.

The coding is summarized in Table 5-4.

2–0

ETRIGCH[2:0]

External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3–0 inputs

as source for the external trigger. The coding is summarized in Table 5-4.

Table 5-4. External Trigger Channel Select Coding

ETRIGSEL

ETRIGCH2

ETRIGCH1

ETRIGCH0

External trigger source is

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ETRIG01

1 Only if ETRIG3–0 input option is available (see device overview chapter), else ETRISEL is

ignored, that means external trigger source is still on one of the AD channels selected by

ETRIGCH2–0

ETRIG11

ETRIG21

ETRIG31

Reserved

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