PC912XDP512F0CALR datasheet(152/1348 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

152

Freescale Semiconductor

4.3.2.16.2

Right Justiﬁed Result Data

4.4

Functional Description

The ATD10B16C is structured in an analog and a digital sub-block.

4.4.1

Analog Sub-block

The analog sub-block contains all analog electronics required to perform a single conversion. Separate

power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.

4.4.1.1

Sample and Hold Machine

The sample and hold (S/H) machine accepts analog signals from the external world and stores them as

capacitor charge on a storage node.

The sample process uses a two stage approach. During the ﬁrst stage, the sample ampliﬁer is used to

quickly charge the storage node.The second stage connects the input directly to the storage node to

complete the sample for high accuracy.

When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue

drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks

and the analog power consumption.

The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA.

76543210

R (10-BIT)

R (8-BIT)

BIT 9 MSB

BIT 8

Reset

00000000

= Unimplemented or Reserved

Figure 4-20. Right Justiﬁed, ATD Conversion Result Register x, High Byte (ATDDRxH)

76543210

R (10-BIT)

R (8-BIT)

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Reset

00000000

= Unimplemented or Reserved

Figure 4-21. Right Justiﬁed, ATD Conversion Result Register x, Low Byte (ATDDRxL)

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