PC912XDP512F0CALR datasheet(327/1348 Pages) FREESCALE

327 / 1348 page

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

327

7.3.2.11

Timer System Control Register 2 (TSCR2)

Read or write: Anytime

All bits reset to zero.

76543210

TOI

000

TCRE

PR2

PR1

PR0

Reset

00000000

= Unimplemented or Reserved

Figure 7-16. Timer System Control Register 2 (TSCR2)

Table 7-14. TSCR2 Field Descriptions

Field

Description

TOI

Timer Overﬂow Interrupt Enable

0 Timer overﬂow interrupt disabled.

1 Hardware interrupt requested when TOF ﬂag set.

TCRE

Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output

compare. This mode of operation is similar to an up-counting modulus counter.

0 Counter reset disabled and counter free runs.

1 Counter reset by a successful output compare on channel 7.

Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register

TC7 = 0xFFFF and TCRE = 1, the TOF ﬂag will never be set when TCNT is reset from 0xFFFF to 0x0000.

2:0

PR[2:0]

Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT

bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized

edge where all prescale counter stages equal zero. See Table 7-15.

Table 7-15. Prescaler Selection

PR2

PR1

PR0

Prescale Factor

128

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