PC912XDP512F0CALR datasheet(214/1348 Pages) FREESCALE

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Chapter 6 XGATE (S12XGATEV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

214

Freescale Semiconductor

6.8.2.5

Bit Field Operations

This addressing mode is used to identify the position and size of a bit ﬁeld for insertion or extraction. The

width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is

ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions

are very useful to extract, insert, clear, set or toggle portions of a 16 bit word.

Figure 6-23. Bit Field Addressing

BFEXT

R3,R4,R5 ; R5: W4 bits offset O4, will be extracted from R4 into R3

6.8.2.6

Special Instructions for DMA Usage

The XGATE offers a number of additional instructions for ﬂag manipulation, program ﬂow control and

debugging:

1. SIF: Set a channel interrupt flag

2. SSEM: Test and set a hardware semaphore

3. CSEM: Clear a hardware semaphore

4. BRK: Software breakpoint

5. NOP: No Operation

6. RTS: Terminate the current thread

W4=3, O4=2

Bit Field Extract

Bit Field Insert

RS2

RS1

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