PC312XDP512F0CFVR datasheet(1269/1348 Pages) FREESCALE

1269 / 1348 page

Appendix A Electrical Characteristics

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1271

And ﬁnally the frequency relationship is deﬁned as

With the above values the resistance can be calculated. The example is shown for a loop bandwidth

fC = 20 kHz:

The capacitance Cs can now be calculated as:

The capacitance Cp should be chosen in the range of:

A.5.3.2

Jitter Information

The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the

deviation from the reference clock fref is measured and input voltage to the VCO is adjusted

accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.

Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock

jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.

Figure A-4. Jitter Deﬁnitions

ζ f

ref

⋅⋅

πζ

⎝⎠

⎛⎞

⋅

-------------------------------------------

-----

ref

410

⋅

-------------

ζ 0.9

()

;

→

⋅

fC < 100kHz

VCO

ref

---------------

synr

()

⋅

= 20

π nf

⋅⋅ ⋅

KΦ

-----------------------------

2 π 20 20kHz

⋅⋅

⋅

539.1Hz

() Ω

⁄

------------------------------------------

4.7kΩ

⋅

π f

⋅⋅

----------------------

0.516

⋅

---------------

ζ 0.9

()

;

= 5.5nF = ~ 4.7nF

------

≤≤

CP = 470pF

N-1

tnom

tmax1

tmin1

tmaxN

tminN

PC312XDP512F0CFVR bảng dữ liệu(PDF) 1269 Page - Freescale Semiconductor, Inc

PC312XDP512F0CFVR bảng dữ liệu(HTML) 1269 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL