PC312XDP512F0CFVR datasheet(1266/1348 Pages) FREESCALE

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Appendix A Electrical Characteristics

MC9S12XDP512 Data Sheet, Rev. 2.21

1268

Freescale Semiconductor

If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and

SCME = 1), the system will resume operation in self-clock mode after tfws.

A.5.1.5

Pseudo Stop and Wait Recovery

The recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in

both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts

fetching the interrupt vector.

A.5.2

Oscillator

The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce

oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce

oscillator/external clock depends on the XCLKS signal which is sampled during reset. Before asserting the

oscillator to the internal system clocks the quality of the oscillation is checked for each start from either

power-on, STOP or oscillator fail. tCQOUT speciﬁes the maximum time before switching to the internal self

clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines

the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A clock monitor

failure is asserted if the frequency of the incoming clock signal is below the assert frequency fCMFA.

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