PC912XDP512F0CFVR datasheet(1297/1348 Pages) FREESCALE

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Appendix D Using L15Y Silicon

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1299

Appendix D

Using L15Y Silicon

The following items should be considerd when using L15Y Silicon:

•

Do not write or read to registers which are marked “Reserved” in Table 1-1.

•

Fill the interrupt vector locations which are marked “Reserved” in Table 1-12. according to your

coding policies for unused interrupts

•

L15Y Silicon includes two analog to digital converters ATD0 and ATD1. ATD0 channels 7 to 0 are

connected to PAD07 to PAD00 and ATD1 channels 7 to 0 are connected to PAD15 to PAD08.

•

L15Y Silicon integrates the S12X_DBG module Version 2. L15Y Silicon integrates the

S12X_MMC module Version 2. This Version doesn’t support the following enhancement which is

available on S12X_MMC Version 3:

— S12XCPU and S12XBDM can access MCU resources which are on different target busses at

the same time. I.E S12XCPU can access XSRAM and S12XBDM can access Register Space

at the same time.

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