PC912XDP512F0CFVR datasheet(120/1348 Pages) FREESCALE

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Chapter 3 Pierce Oscillator (S12XOSCLCPV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

120

Freescale Semiconductor

3.1.3

Block Diagram

Figure 3-1 shows a block diagram of the XOSC.

Figure 3-1. XOSC Block Diagram

3.2

External Signal Description

This section lists and describes the signals that connect off chip

3.2.1

VDDPLL and VSSPLL — Operating and Ground Voltage Pins

Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This

allows the supply voltage to the XOSC to be independently bypassed.

3.2.2

EXTAL and XTAL — Input and Output Pins

These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal

clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator ampliﬁer.

XTAL is the output of the crystal oscillator ampliﬁer. The MCU internal system clock is derived from the

EXTAL

XTAL

Gain Control

VDDPLL = 2.5 V

OSCCLK

Monitor_Failure

Clock

Monitor

Peak

Detector

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